This invention relates to a ramp type analog-to-digital converter (hereinafter referred to as an A-D converter), and more particularly to a simple-structured but highly accurate A-D converter.
As a system of a ramp type A-D converter, there has been proposed a dual integration type A-D converter. In the dual integration type A-D converter, an analog voltage to be converted is subjected to first integration by an analog integrator for a predetermined period of time and, after the lapse of the period, the supply of the analog voltage to be converted is cut off and a reference voltage E.sub.0 reverse in polarity from the analog voltage is subjected to second integration by the analog integrator. At the same time, clock pulses of a known frequency are applied to a counter and, at a moment when the integrated voltage of the analog integrator has returned to its initial reference value, the supply of the clock pulses to the counter is stopped. At this time, the count value of the counter corresponds to the analog voltage to be converted and a digital value is derived from the count value of the counter.
In the dual integration type A-D converter, the moment of termination of the second integration does not always coincide with the clock pulse, resulting in a minute error which depends on the clock pulse interval. A method for converting the minute error to digital form with high resolution is disclosed, for example, in U.S. Pat. No. Re. 28,706 (reissued Feb. 3, 1976). According to this method, reference voltage E.sub.1 which has a certain magnitude and is opposite in polarity to an integrated output is abruptly provided at the beginning of the second integration and the second integration is completed in synchronism with a clock pulse immediately after the integrated voltage of the integrator has passed the original reference value E.sub.0. Upon completion of the second integration, another abrupt voltage -E.sub.1 of the same magnitude as the aforesaid voltage E.sub.1 but opposite in polarity thereto is applied to the output side of the integrator and the resulting voltage is subjected to a third integration until it returns to the reference value E.sub.0. The third integration is carried out at a speed 1/10 that of the second integration and the counting of the clock pulses by the counter at its counting stage is of one lower order. As a result of this, the minute error occurring at the end of the second integration is converted to digital form during the third integration thus providing for enhanced accuracy in the A-D conversion of lower order digits.
The above triple integration system requires the first and second abrupt voltages E.sub.1 and -E.sub.1 in addition to the positive and negative reference voltages needed for the second integration. The abrupt voltages E.sub.1 and -E.sub.1 must be reverse in polarity from each other and exactly equal in absolute value to each other. A circuit for producing these voltages is difficult to obtain and expensive. Furthermore, since this system involves addition and subtraction of analog signals for the triple integration, a switching circuit that is used is complicated in construction, inevitably resulting in the manufacturing cost becoming high.
It is an object of the present invention to provide an A-D converter which does not require an abrupt voltage source but is capable of obtaining accuracy equal to or higher than that obtainable with the abovesaid triple integration type A-D converter.